Each clock edge is referred to as a beat, with two beats (one upbeat and one downbeat) per cycle. Relation of bandwidth and frequency ĭescribing the bandwidth of a double-pumped bus can be confusing. This tactic was chosen by InfiniBand and PCI Express. The two technologies are independent of each other and many motherboards use both, by using DDR memory in a dual channel configuration.Īn alternative to double or quad pumping is to make the link self-clocking. ĭDR should not be confused with dual channel, in which each memory channel accesses two RAM modules simultaneously. It is more recently being used for other systems with high data transfer speed requirements – as an example, for the output of analog-to-digital converters (ADCs).
This technique has been used for microprocessor front-side busses, Ultra-3 SCSI, expansion buses ( AGP, PCI-X ), graphics memory ( GDDR), main memory (both RDRAM and DDR1 through DDR5), and the HyperTransport bus on AMD's Athlon 64 processors. By using both edges of the clock, the data signals operate with the same limiting frequency, thereby doubling the data transmission rate. When operating at a high bandwidth, signal integrity limitations constrain the clock frequency. This, however, requires that the clock signal changes twice per transfer, while the data lines change at most once per transfer.
The simplest way to design a clocked electronic circuit is to make it perform one transfer per full cycle (rise and fall) of a clock signal. The term toggle mode is used in the context of NAND flash memory.
This is also known as double pumped, dual-pumped, and double transition. In computing, a computer bus operating with double data rate ( DDR) transfers data on both the rising and falling edges of the clock signal. A comparison between single data rate, double data rate, and quad data rate
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